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Ordering number :EN4846A
CMOS IC
LC74761, 74761M
On-Screen Display LSI
Overview
The LC74761 and LC74761M are on-screen display CMOS LSIs that superimpose text and low-level graphics onto a TV screen (video signal) under microcontroller. The display characters have a 12 by 18 dots structure, and 256 characters are provided.
Package Dimensions
unit: mm 3196-DIP30SD
[LC74761]
Features
* Display structure: 12 lines by 24 characters (up to 288 characters) * Maximum character display: Up to 288 characters * Character configuration: 12 (W) by 18 (H) dots structure * Number of characters: 256 characters (254 plus space 1 font and transparent space 1 font) * Character sizes: Three sizes (normal, double, and triple sizes) * Display starting positions: 64 horizontal and 64 vertical locations * Reverse video function: Characters can be inverted on a per character basis. * Flashing types: Two types with periods of 0.5 and 1.0 second on a per character basis (duty fixed at 50%) * Background color: One of eight colors (when internal synchronization used) * External control input: Serial data input in 8-bit units * Built-in horizontal/vertical sync separation circuit, AFC circuit, and synchronization detector * Video output: Composite video signal output in NTSC, PAL, PAL-M, PAL-N, PAL60, NTSC4.43, or SECAM format
SANYO: DIP30SD
unit: mm 3216A-MFP30S
[LC74761M]
SANYO: MFP30S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
13096HA (OT)/N2894TH (OT) No. 4846-1/20
LC74761, 74761M
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Pd max Topr Tstg VDD1, VDD2 pins All input pins HSYNCOUT, VSYNCOUT, SYNCDET pins Conditions Ratings VSS - 0.3 to VSS + 7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 300 -30 to +70 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges at Ta = -30 to +70C
Parameter Supply voltage Symbol VDD1 VDD2 VIH1 Input high level voltage VIH2 VIL1 Input low level voltage Input voltage Composite video signal input voltage VIL2 VIN VIN1 VIN2 VIN3 VDD1 pin VDD2 pin RST, CS, SIN, SCLK pins SECAM, 525/625, NTSC/PAL, 3.58/4.43 pins RST, CS, SIN, SCLK pins SECAM, 525/625, NTSC/PAL, 3.58/4.43 pins FC, AMPIN pins CVIN pins CVCR pins SYNCIN pins NTSC Oscillator frequency FOSC1 XtalIN1, XtalOUT1, XtalIN2, XtalOUT2 pins; 4fsc PAL PAL-M PAL-N Conditions Ratings min 4.5 4.5 0.8 VDD1 0.7 VDD1 VSS - 0.3 VSS - 0.3 VSS - 0.3 2 VPP 2 VPP 2 VPP 14.318 17.734 14.302 14.328 2.5 VPP typ 5.0 5.0 max 5.5 1.27 VDD1 VDD1 + 0.3 VDD1 + 0.3 0.2 VDD1 0.3 VDD1 VDD1 + 0.3 Unit V V V V V V V V V V MHz MHz MHz MHz
Electrical Characteristics at Ta = -30 to +70C, with VDD1 = VDD2 = 5 V unless otherwise specified
Parameter Output off leakage current Input off leakage current Symbol Ileak1 Ileak2 VOH CVOUT pin CVIN, CVCR pins HSYNCOUT, VSYNCOUT, SYNCDET, SECAM, 525/625, NTSC/PAL, 3.58/4.43, AMPOUT, PDOUT pins; VDD1 = 4.5 V, IOH = -1.0 mA HSYNCOUT, VSYNCOUT, SYNCDET, SECAM, 525/625, NTSC/PAL, 3.58/4.43, AMPOUT, PDOUT pins; VDD1 = 4.5 V, IOL = 1.0 mA RST, CS, SIN, SCLK, SECAM, 525/625, NTSC/PAL, 3.58/4.43 pins; VIN = VDD1 SECAM, 525/625, NTSC/PAL, 3.58/4.43 pin; VIN = VSS1 VCOIN, VCOOUT pins; FC = 1/2 VDD1 VDD1 pin; All outputs open, Xtal: 4fsc VDD2 pin; VDD2 = 5.0 V -1 14.12 15 20 3.5 Conditions Ratings min typ max 10 10 Unit A A
Output high level voltage
V
Output low level voltage
VOL
1.0
V
IIH Input current IIL Oscillator frequency Operating current dissipation FOSC3 IDD1 IDD2
1
A A MHz mA mA
Timing Characteristics at Ta = -30 to +70C, VDD = 5 0.5 V
Ratings Parameter Minimum input pulse width Data setup time Data hold time One word write time Symbol tW(SCLK) tW(CS) tSU(CS) tSU(SIN) th(CS) th(SIN) tword twt SCLK pin CS pin (during periods when CS is high) CS pin SIN pin CS pin SIN pin Write time for 8 bits of data RAM data write time Conditions min 200 1 200 200 2 200 4.2 1 typ max Unit ns s ns ns s ns s s
No. 4846-2/20
LC74761, 74761M
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 Symbol VSS XtalIN1 XtalOUT1 HSYNCOUT XtalIN2 XtalOUT2 VSYNCOUT CS SIN SCLK SECAM Vertical synchronization output Enable input Data input Clock input SECAM mode switch input/ output (command switch) 525/625 switch input/output (command switch) NTSC/PAL switch input/output (command switch) Horizontal synchronization output Crystal oscillator connection Ground Crystal oscillator connection Function Ground connection Connection for the crystal and capacitor used to form the crystal oscillator that generates the internal synchronization signal. The oscillator can be selected with a command switch. Outputs the horizontal synchronization signal (AFC). The output polarity can be selected (metal option). Also functions as general output port (command switch). Connection for the crystal and capacitor used to form the crystal oscillator that generates the internal synchronization signal. Outputs the vertical synchronization signal. The output polarity can be selected (metal option). Also functions as general output port (command switch). Enables/disables serial data input. Serial data is enabled when this pin is low (hysteresis input). Pull-up resistor built in (metal option). Serial data input (hysteresis input). Pull-up resistor built in (metal option). Clock input for serial data input (hysteresis input). Pull-up resistor built in (metal option). During input, switches between SECAM and other modes. During output, functions as general output port or internal V output (command switch). Low = other modes, high = SECAM mode During input, switches between 525 scan lines and 625 scan lines. During output, functions as general output port or character data output (command switch). Low = 525 lines, high = 625 lines Switches the color mode between NTSC and PAL. During output, functions as general output port or frame data output (command switch). Low = NTSC, high = PAL Switch FSC between 3.58 MHz and 4.43 MHz. During output, functions as general output port or half-tone output (command switch). Low = 3.58, high = 4.43 System reset input pin, low is active (hysteresis input). Pull-up resistor built in (metal option). Composite video output Power supply connection for composite video signal level generation Composite video input SECAM chroma signal input Built-in sync separator circuit video signal input Built-in sync separator circuit Ground connection AFC control voltage output Filter connection AFC control voltage input VCO LC oscillator circuit coil and capacitor connection Outputs the exclusive NOR of the horizontal synchronization signal (AFC) and CSYNC (sync separator). The output polarity can be selected (metal option). Also functions as general output port (command switch). Power supply connection (+5 V: digital system power supply) Description
12
525/625
13
NTSC/PAL
14
3.58/4.43
3.58/4.43 switch input/output (command switch) Reset input Video signal output Power supply connection Video signal input Video signal input Sync separator circuit input Sync separator circuit Ground Control voltage output AFC filter connection Control voltage input LC oscillator connection External synchronization signal detection output Power supply connection
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
RST CVOUT VDD2 CVIN CVCR SYNCIN SEPC VSS PDOUT AMPIN AMPOUT FC VCOIN VCOOUT SYNCDET VDD1
No. 4846-3/20
LC74761, 74761M
Pin Assignment
Top view
Serial Data Input Timing
No. 4846-4/20
LC74761, 74761M
System Block Diagram
No. 4846-5/20
LC74761, 74761M
Display Control Commands
Display control commands are input in an 8-bit serial format. Commands consist of a command identification code in the first byte and data in the second and following bytes. The following commands are supported. 1 2 3 4 5 6 7 8 COMMAND0: COMMAND1: COMMAND2: COMMAND3: COMMAND4: COMMAND5: COMMAND6: COMMAND7: Display memory (VRAM) write address setting command Display character data write command Vertical display start position and character size (lines 1 and 2) setting command Horizontal display start position and character size (lines 9 and 11) setting command Display control setting command 1 Display control setting command 2 Display control setting command 3 Display control setting command 4
Display Control Command Table
First byte Command Command identification code 7 COMMAND0 Write address COMMAND1 Character write COMMAND2 Vertical display start position COMMAND3 Horizontal display start position COMMAND4 Display control 1 COMMAND5 Display control 2 COMMAND6 Display control 3 COMMAND70 Display control 4 COMMAND71 Display control 5 COMMAND72 Display control 6 COMMAND73 Display control 7 1 1 1 1 1 1 1 1 1 1 1 6 0 0 0 0 1 1 1 1 1 1 1 5 0 0 1 1 0 0 1 1 1 1 1 4 0 1 0 1 0 1 0 1 1 1 1 3 V3 0 SZ 21 SZ B1 RST PH 2 2 V2 0 SZ 20 SZ B0 RAM PH 1 Data 1 V1 at2 SZ 11 SZ 91 OSC PH 0 0 V0 at1 SZ 10 SZ 90 RND I/E 7 0 c7 0 0 0 0 0 0 0 0 0 6 0 c6 0 0 I/N TST HFI VCOS 1 EG 2 0 0 5 0 c5 VP 5 HP 5 BLK 1 CHAL 4 H4 c4 VP 4 HP 4 BLK 0 BLK Second byte Data 3 H3 c3 VP 3 HP 3 BK 1 RSL 1 IOS LIN 3 VMN 2 H2 c2 VP 2 HP 2 ATS RSL 0 BCL 1 LIN 2 SVIS 1 H1 c1 VP 1 HP 1 0 CVM BCL 0 LIN 1 VNS 0 H0 c0 VP 0 HP 0 DSP XTS CB LIN 0 VSS
MOD MOD MOD MOD 3 2 1 0 0 0 1 1 0 1 0 1 0 0 0 0 LINS LINS LINS LINS
M30S SMS LIN 5 PS 2 0 0 LIN 4 PS 1 0 0
MOD MOD MOD MOD 3 2 1 0 VCOS SOUT VOUT HOUT 2
Once the command identification code in the first bite is written, it is stored internally until the first byte of the following command is written. However, when the display character data write command (COMMAND1) is written, the system becomes locked in display character data write mode, and the first byte cannot be overwritten. When the CS pin is set high the command state is set to COMMAND0, i.e., display memory write address setting mode.
No. 4846-6/20
LC74761, 74761M 1 COMMAND0: Display Memory Write Address Setting Command
First data byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- V3 State 1 0 0 0 0 1 0 1 0 1 0 1 Display memory line address (from 0 to B (hexadecimal)) The command 0 identification code: sets the display memory write address. Function Note
2
V2
1
V1
0
V0
Second byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- H4 State 0 0 0 0 1 0 1 0 1 0 1 0 1 Display memory character address (from 0 to 17 (hexadecimal)) Function Second byte identification code Note
3
H3
2
H2
1
H1
0
H0
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
2
COMMAND1: Display Character Data Write Setting Command
First byte
Register content DA0 to DA7 7 6 5 4 3 2 1 Register name -- -- -- -- -- -- at2 State 1 0 0 1 0 0 0 1 0 1 Turns character attribute 2 off. Turns character attribute 2 on. Turns character attribute 1 off. Turns character attribute 1 on. Specifies highlight or flashing. The command 1 identification code: sets the display memory write address. When this command is entered, the chip locks in display character write mode until the CS pin is set high. Function Note
0
at1
Specifies reverse video.
No. 4846-7/20
LC74761, 74761M Second byte
Register content DA0 to DA7 7 Register name c7 State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Character code (from 00 to FF (hexadecimal)) Function Note
6
c6
5
c5
4
c4
3
c3
2
c2
1
c1
0
c0
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
3
COMMAND2: Vertical Display Position Setting Command
First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- SZ21 State 1 0 1 0 0 1 0 1 0 1 0 1 SZ11 0 1 SZ21 0 1 SZ10 SZ20 0 Normal size Triple size 0 Normal size Triple size 1 Double size Normal size 1 Double size Normal size Character size for the first line Character size for the second line The command 2 identification code: sets the vertical display position. Function Note
2
SZ20
1
SZ11
0
SZ10
Second byte
Register content DA0 to DA7 7 6 5 Register name -- -- VP5 (MSB) VP4 State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 The vertical display start position is given by VS = H x (
5
Function Second byte identification code
Note
2nVPn)
4
n=0
where H is the horizontal synchronization pulse period. The six bits VP0 to VP5 specify the vertical display start position. The weight of the lsb is 1 x H.
3
VP3
2
VP2
1
VP1 VP0 (LSB)
0
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
No. 4846-8/20
LC74761, 74761M 4 COMMAND3: Horizontal Display Position Setting Command
First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- SZB1 State 1 0 1 1 0 1 0 1 0 1 0 1 SZ91 0 1 SZB1 0 1 SZ90 SZB0 0 Normal size Triple size 0 Normal size Triple size 1 Double size Normal size 1 Double size Normal size The character size for the ninth line. The character size for the eleventh line. The command 3 identification code: sets the horizontal display position. Function Note
2
SZB0
1
SZ91
0
SZ90
Second byte
Register content DA0 to DA7 7 6 5 Register name -- -- HP5 (MSB) HP4 State 0 0 0 1 0 1 0 1 0 1 0 1 0 1 HS = Tc x (
5
Function Second byte identification code
Note
4
The horizontal display start position is given by 2nHPn) The six bits HP0 to HP5 specify the vertical display start position. The weight of the lsb is 1 x Tc.
3
HP3
n=0
2
HP2
where Tc is the period of the OSCIN and OSCOUT oscillator in operating mode.
1
HP1 HP0 (LSB)
0
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
5
COMMAND4: Display Control Setting Command 1
First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- RSTSYS State 1 1 0 0 0 1 0 2 RAMERS 1 0 1 0 1 Erases display RAM. (Sets display RAM to FF (hexadecimal).) Continues crystal oscillator operation. Stops the crystal oscillator. Turns off rounding. Turns on rounding. Resets all registers. (Clears all registers to 0.) This reset occurs when the CS pin goes low, and the reset state cleared when the CS pin goes high. The RAM erase function requires at least 500 s. It is executed on DSPOFF. Only valid with character display off if external synchronization is used. Only valid for double and triple size characters. The command 4 identification code: sets display control parameters. Function Note
1
OSCSTP RNDSEL
0
No. 4846-9/20
LC74761, 74761M Second byte
Register content DA0 to DA7 7 6 Register name -- INT/NON State 0 0 1 0 1 0 1 0 1 0 1 0 0 1 Character display off Character display on Turns character output on and off. BLK1 0 1 Function Second byte identification code Interlaced Non-interlaced BLK0 0 Blanking off Frame size blanking 1 Character size blanking Total area blanking Sets the flashing period. Changes the blanking size. Switches between interlaced and non-interlaced display. Note
5
BLK1
4
BLK0
3
BK1
Flashing period about 0.5 s Flashing period about 1 s Highlight function Flashing function
2 1 0
ATS -- DSPON
Selects at2.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
6 COMMAND5: Display Control Setting Command 2 First byte
Register content DA0 to DA7 7 6 5 4 Register name -- -- -- -- State 1 1 0 1 0 3 PH2 1 0 0 2 PH1 1 0 1 PH0 1 0 INT/EXT 0 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 PHASE 2 PHASE 1 PHASE 0 Background color (phase) NTSC /2 In phase 3 /2 3 /4 /4 7 /4 5 /4 PAL /2 In phase /2 3 /4 /4 /4 3 /4 Switches between internal and external synchronization. Sets the phase of the background color for color burst.sz The command 5 identification code: sets display control parameters. Function Note
External synchronization mode Internal synchronization mode
No. 4846-10/20
LC74761, 74761M Second byte
Register content DA0 to DA7 7 6 Register name -- TST State 0 0 1 0 5 CHAL 1 0 4 BKL 1 0 3 RSL1 1 0 2 RSL0 1 0 1 0 1 Function Second byte identification code Normal operation Test mode Sets the character intensity level to about 85 IRE (bright white). Sets the character intensity level to about 72 IRE (white with a touch of grey). Sets the blanking intensity level to about 3 IRE (a deep black as a frame level). Sets the blanking intensity level to about 13 IRE (a dark grey as a frame level). RSL1 0 0 1 1 RSL0 0 1 0 1 Intensity level About 15 IRE About 30 IRE About 45 IRE About 55 IRE Amplitude About 60 IRE About 60 IRE About 60 IRE About 65 IRE Switches the background intensity level. Switches the blanking intensity level. Switches the character intensity level. Test mode should not be used. This bit should always be zero. Note
1
CVoutmt
Normal CVout output CVout pedestal level output Selects XTAL1 Selects XTAL2 Switches the oscillator circuit
0
XTALsel
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
7
COMMAND6: Display Control Setting Command 3
First byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- MOD3 State 1 1 1 0 0 1 0 2 MOD2 1 0 1 MOD1 1 0 1 Sets Fsc to 3.58 MHz. Sets Fsc to 4.43 MHz. Sets the color mode to NTSC. Sets the color mode to PAL. Sets the number of scan lines to 525 lines. Sets the number of scan lines to 625 lines. Sets the mode to a mode other than SECAM. Sets the mode to SECAM mode. The logical or of this bit and the Fsc switching input pin (pin 14) is used. The logical or of this bit and the color mode switching input pin (pin 13) is used. The logical or of this bit and the scan line count switching input pin (pin 12) is used. The logical or of this bit and the mode switching input pin (pin 11) is used. The command 6 identification code: sets display control parameters. Function Note
0
MOD0
No. 4846-11/20
LC74761, 74761M Second byte
Register content DA0 to DA7 7 6 Register name -- HALF INT P14OUT SEL SECAM SEL IOS State 0 0 1 0 1 0 1 0 1 0 2 BCOL1 1 0 1 BCOL0 1 0 1 Function Second byte identification code Normal mode Half internal synchronous mode Half tone output High output in internal synchronous mode In SECAM mode, only the character frame area is on. In SECAM mode, the entire character display area is on. Sets the mode setting pin to be an input pin. Sets the mode setting pin to be an output pin. BCOL1 0 0 1 1 BCOL0 0 1 0 1 Background color Background color displayed No background color (about 13 IRE) No background color (about 23 IRE) CVoutmt2 (CSYNC) Only valid when either BCOL0 is 1 or BCOL1 is 1. Determines whether a background color is displayed. (Only valid in internal synchronization mode.) Selects P14 (3.58/4.43) output. Note
5
4
Selects the CVCR "on" period. Switches the input/output direction of the mode setting pins.
3
0
CBOFF
Outputs a color burst signal. Stops the output of color burst signals.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
8
COMMAND70: Display Control Setting Command 4
First byte
Register content DA0 to DA7 7 6 5 4 3 2 1 0 Register name -- -- -- -- -- -- -- LINS State 1 1 1 1 0 0 0 0 1 Selects the lower 6 bits (bits 0 to 5) Selects the upper 6 bits (bits 6 to B) Selects the upper or lower six bits when halftone output line mode is specified. Expansion command 0 identification code The command 7 identification code: sets display control parameters. Function Note
Second byte
Register content DA0 to DA7 7 6 Register name -- VCO SELECT1 LIN5 State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Second byte identification code VCO frequency is 14.12 MHz VCO frequency is 7.07 MHz Turns off (low) sixth line halftone output. Turns on (high) sixth line halftone output. Turns off (low) fifth line halftone output. Turns on (high) fifth line halftone output. Turns off (low) fourth line halftone output. Turns on (high) fourth line halftone output. Turns off (low) third line halftone output. Turns on (high) third line halftone output. Turns off (low) second line halftone output. Turns on (high) second line halftone output. Turns off (low) first line halftone output. Turns on (high) first line halftone output. Selects VCO oscillation frequency. Used for the line 12 setting when LINS is high. Used for the line 11 setting when LINS is high. Used for the line 10 setting when LINS is high. Used for the line 9 setting when LINS is high. Used for the line 8 setting when LINS is high. Used for the line 7 setting when LINS is high. Note
5
4
LIN4
3
LIN3
2
LIN2
1
LIN1
0
LIN0
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
No. 4846-12/20
LC74761, 74761M 9 COMMAND71: Display Control Setting Command 5
First byte
Register content DA0 to DA7 7 6 5 4 3 2 1 0 Register name -- -- -- -- -- -- -- LINS State 1 1 1 1 0 1 0 0 1 Selects lower 6 bits (0 to 5). Selects upper 6 bits (6 to B). Selects lower or upper 6 bits for half tone output line setting. Expansion command 1 identification code The command 7 identification code: sets display control parameters Function Note
Second byte
Register content DA0 to DA7 7 6 Register name -- EGMODE 2SELECT PORTSET SELECT2 PORTSET SELECT1 VMN SEL VINPsel State 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Second byte identification bit Normal display Apply frame to inverted characters also. Set port output data Set port (output switching) Set port output data Set port (output switching) Normal V signal VMASK signal Normal I/O V is input from P11. V rise detection V fall detection VSEP is about 9.3 s. VSEP is about 18.6 s. Selects V detection polarity. Note
5
4
3
2
1
VNPsel
0
VSEPsel
Selects V separation time.
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
10 COMMAND72: Display Control Setting Command 6 First byte
Register content DA0 to DA7 7 6 5 4 3 2 1 0 Register name -- -- -- -- -- -- -- LINS State 1 1 1 1 1 0 0 0 1 Selects lower 6 bits (0 to 5). Selects upper 6 bits (6 to B). Selects lower or upper 6 bits for half tone output line setting. Expansion command 2 identification code The command 7 identification code: sets display control parameters Function Note
No. 4846-13/20
LC74761, 74761M Second byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- MOD3 SEL MOD2 SEL MOD1 SEL MOD0 SEL State 0 0 0 0 0 1 0 1 0 1 0 1 Normal MOD3 (P14) output (PS1 = 1) Specifies MOD3 general port output Normal MOD2 (P13) output (PS1 = 1) Specifies MOD2 general port output Normal MOD1 (P12) output (PS1 =1) Specifies MOD1 general port output Normal MOD0 (P11) output (PS1 = 1) Specifies MOD0 general port output Specifies port output data when PS1 = 0. Specifies port output data when PS1 = 0. Specifies port output data when PS1 = 0. Specifies port output data when PS1 = 0. Function Second byte identification bit Note
2
1
0
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
11 COMMAND73: Display Control Setting Command 7 First byte
Register content DA0 to DA7 7 6 5 4 3 2 1 0 Register name -- -- -- -- -- -- -- LINS State 1 1 1 1 1 1 0 0 1 Selects lower 6 bits (0 to 5). Selects upper 6 bits (6 to B). Selects lower or upper 6 bits for half tone output line setting. Expansion command 3 identification code The command 7 identification code: sets display control parameters Function Note
Second byte
Register content DA0 to DA7 7 6 5 4 3 Register name -- -- -- -- VCP SELECT2 SDETOUT SEL VOUT SEL HOUT SEL State 0 0 0 0 0 1 0 1 0 1 0 1 No feedback resistance Feedback resistance Normal SOUT (P29) output (PS2 = 1) Specifies SOUT general port output Normal VOUT (P7) output (PS2 =1) Specifies VOUT general port output Normal HOUT (P4) output (PS2 = 1) Specifies HOUT general port output Specifies VCO oscillator feedback resistance connection Specifies port output data when PS2 = 0. Specifies port output data when PS2 = 0. Specifies port output data when PS2 = 0. Function Second byte identification bit Note
2
1
0
Note: When the chip is reset by the RST pin, the register states (bits) are all cleared to 0.
No. 4846-14/20
LC74761, 74761M
Display Configuration
The display consists of 12 rows of 24 characters each. Up to 288 characters can be displayed unless enlarged characters are displayed. Display memory addresses are expressed as a row address in the range 0 to B (hexadecimal) and a column address in the range 0 to 17 (hexadecimal).
Display Configuration and Display Memory Addresses
24 characters by 12 rows
No. 4846-15/20
LC74761, 74761M
Output level 2.638 2.449 2.262 2.047 1.747 1.610
Output voltage (VDC)
Output level Frame level 1 Pedestal level Background low level 1 Burst low level Sync level
Output voltage (VDC) 1.465 1.429 1.212 1.080 0.800
Character level 1
Composite Video Signal Output Levels (internally generated levels) Metal Option
Character level 2
Background high level 2
Background high level 1
Burst high level
No. 4846-16/20
Frame level 2
LC74761, 74761M
Output level 2.841 2.652 2.456 2.242 1.943 1.811
Output voltage (VDC)
Output level Frame level 1 Pedestal level Background low level 1 Burst low level Sync level
Output voltage (VDC) 1.665 1.624 1.407 1.275 1.000
Character level 1
Composite Video Signal Output Levels (internally generated levels) Metal Option
Character level 2
Background high level 2
Background high level 1
Burst high level
No. 4846-17/20
Frame level 2
LC74761, 74761M
Output level 3.342 3.153 2.950 2.735 2.436 2.312
Output voltage (VDC)
Output level Frame level 1 Pedestal level Background low level 1 Burst low level Sync level
Output voltage (VDC) 2.166 2.118 1.902 1.770 1.500
Character level 1
Composite Video Signal Output Levels (internally generated levels) Metal Option
Character level 2
Background high level 2
Background high level 1
Burst high level
No. 4846-18/20
Frame level 2
LC74761, 74761M
Application Circuit Diagram
Signal format NTSC PAL SECAM PAL-M PAL-N NTSC4.43
4 Fsc (MHz) 3.579545 x 4 4.433618 x 4 4.433618 x 4 3.575611 x 4 3.582056 x 4 4.433618 x 4
Signal format NTSC PAL SECAM PAL-M PAL-N NTSC4.43
SW1 0 0 1 0 0 0 0
SW2 0 1 (1) 0 1 0 0
SW3 0 1 (1) 1 1 0 1
SW4 0 1 (1) 0 0 1 1
PAL60 4.433618 x 4 PAL60 Note: Fix SW1 to SW4 to 0 when setting a mode by command.
No. 4846-19/20
LC74761, 74761M
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January 1996. Specifications and information herein are subject to change without notice. PS No. 4846-20/20

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